1. Field of the Invention
The invention relates to a level converter apparatus for converting an original voltage level to a wanted voltage level and, more particularly, to a signal converting system having a level converter for high-speed semiconductor devices and a signal converting method therefor.
2. Description of the Related Art
With the reduction in design rules for semiconductor memory devices, voltage levels in semiconductor chips have been greatly reduced. Interface voltage levels, however, which are determined for interfaces between the internal circuitry of a chip and an external circuit, have not been significantly reduced for reasons of signal transfer characteristics and interface efficiency.
Referring to FIG. 1, an internal voltage of a chip tends to be determined at lower levels than the corresponding interface voltage. The graphed line G1 illustrates interface voltage levels and G2 indicates internal voltage levels. The transverse axis indicates design rules and vertical axis indicates voltage levels. Comparing the graphs G1 and G2 indicates that the internal voltage levels are lower than the interface voltage levels when the design rules are in the range of point t1 and below as design rules are reduced. Accordingly, in the case where an internal voltage level is lower than an interface voltage level, a level converter for increasing a voltage level of an output signal needs to be employed in a semiconductor device in order to output an internal signal of chip to an external circuit.
Referring to FIG. 2, there is shown a typical voltage level converter, which is used as a data output buffer. This level converter includes PMOS transistor pair P1, P2 in which gate terminals each are cross-coupled to the other""s corresponding drain terminals, NMOS transistors N1, N2 having their drain terminals connected to the drain terminals of the PMOS transistor pair P1, P2 and wherein their gate terminals receive an input signal DIN and an inverted input signal, a first inverter I1 for receiving a first power voltage VDD as an operational power voltage and inverting a level of the input signal DIN, and a second inverter I2 for receiving a second power voltage vddq as an operational power voltage and connected to a drain terminal of the PMOS transistor P2 to thereby invert a signal level of an output node NO2. The level of the first power voltage VDD at DIN is lower than that of the second power voltage vddq and corresponds to an internal voltage level. The level of the second power voltage vddq corresponds to the interface voltage level. The level converter operates as follows in order to convert an input signal having an internal voltage level to an output signal having an interface voltage level.
When the input signal DIN is input as a CMOS logic level xe2x80x9chighxe2x80x9d, the NMOS transistor N1 is turned on and the other NMOS transistor N2 is turned off. Accordingly, the PMOS transistor P1 is turned off and a gate voltage of the PMOS transistor P2 decreases to 0V, and the PMOS transistor P2 is turned on. As a result, the node NO2 goes to logical xe2x80x9chighxe2x80x9d by being affected by a level of the second power voltage vddq. The xe2x80x9chighxe2x80x9d level of the node NO2 is inverted by the second inverter I2 and output as a xe2x80x9clowxe2x80x9d level at the output terminal DOUT. The xe2x80x9clowxe2x80x9d level at the output terminal DOUT is approximately 0V.
When the input signal DIN is input as a logic xe2x80x9clowxe2x80x9d, the NMOS transistor N1 is turned off and another NMOS transistor N2 is turned on. Accordingly, the PMOS transistor P1 is turned on and the gate voltage of the PMOS transistor P2 rises up to a level of the second power voltage vddq, thereby the PMOS transistor P2 is turned off. As a result, the voltage level of the node NO2 goes xe2x80x9clowxe2x80x9d. The xe2x80x9clowxe2x80x9d level of the node NO2 is inverted by the second inverter I2 and output as a xe2x80x9chighxe2x80x9d level at the output terminal DOUT. The xe2x80x9clowxe2x80x9d level at the output terminal DOUT is equal to the interface voltage level. In such a process, an input signal having an amplitude of 0V/VDD is converted to an output signal having an amplitude of vddq/0V.
However, there is a problem. Because the level converter shown in FIG. 2 has converter characteristics as graphed in FIG. 3, it is difficult to apply such a level converter to a semiconductor device having high speed operations. FIG. 3 shows waveforms of input/output signals, the time D that it takes to create the output signal DOUT after the input signal DIN is applied is too long for high speed operations. The delayed time D is caused by the operational characteristics of such static circuits. Such a static circuit requires an overlap time that is caused by the fighting of pull down and pull up currents when a signal is shifted. Such an overlap time causes delay in its operation and deteriorates high-speed responses accordingly. In addition, as shown in FIG. 3, although the pulse duty ratio of the input signal is 50%, the xe2x80x9clowxe2x80x9d region T1 and the xe2x80x9chighxe2x80x9d region T2 are different from one another, which is caused by characteristic of differential amplification type of level converter. The reason is that when a signal is shifted from xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d and a signal is shifted from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d, their response characteristics differ from one another. Hence, the period of time that it takes the level converter in FIG. 2 to convert levels is relatively long and there is accordingly a problem that the duty ratio of an output signal is different from that of an input signal.
The U.S. Pat. No. 6,175,248 to Michael P. Mack, which is issued on Jan. 16, 2001, discloses a logic level converter. The Mack patent is directed to a pulse width distortion correction logic level converter for converting a small swing differential logic signal into full swing complementary CMOS signal while preserving the pulse width of the original signal. The converter includes a receiver circuit for receiving the differential input signal and a converter circuit for converting the differential input signal to first and second output signals and comprising a latch device for latching the first and second output signals to output a single-ended signal having a same pulse width as the differential input signal.
However, the level converter as described in the Mack patent has the disadvantage that, because the converter performs setting and resetting a latch by using first and second output signals (e.g., long pulses having long delay) of the first and second converters receiving a common differential input signal, it takes a long time in a level-converting operation. The reason is that the first and second converters each have delay times of T1 and T2 relative to a rising signal and a falling signal, and the latch receives only a rising signal from the first and second converters to thereby perform set and reset operations. Accordingly, there is a disadvantage that because performance of a chip may be lowered when the above-conventional level converter is employed in a semiconductor device, a conventional level converter is not appropriate for a semiconductor device that requires a high-speed response in its operation.
An object of the invention is to provide a high-speed level converter for converting level in high speed.
Another object of the invention is to provide a level converter minimizing a decrease in performance of a chip.
Another object of the invention is to provide a signal converting apparatus by which the period of time being spent in level converting is minimized and a duty ratio of a level-converted signal becomes identical to a duty ratio of an input signal.
Another object of the invention is to provide a signal converting apparatus and a signal level converting method thereof for outputting a single ended signal having the same pulse width as that of an input signal.
Another object of the invention is to provide a level converter and a level converting method that is appropriate for a high-speed semiconductor device requiring a high-speed response characteristic.
Another object of the invention is to provide a signal converting apparatus and a signal converting method thereof which are appropriate for a high-speed semiconductor memory device requiring a high-speed response characteristic and generates a level-converted output signal having the same pulse width as that of a differential input signal.
According to an aspect of the invention to accomplish the above-objects, a level converter comprises a converting part for outputting a level-converting signal having a different level from that of an input signal in response to an input signal, a delay part for delaying the level converting signal of the converting part by a predetermined time, and a self-reset part for generating a reset signal in response to the delayed level converting signal of the delay part to output it to the converting part so that a pulse width of the level converting signal as output is set as much as the sum of the predetermined delay time and an internal operation delay time.
According to an aspect of the invention, a signal converting apparatus for converting a first input signal and a second input signal that are input as differential input signals comprises a first converter for converting the first input signal to output it, a second converter for converting the second input signal to output it, and a latch part for outputting a single ended signal having the same pulse width as that of the differential input signal in response to the first and second converting signals.
According to an aspect of the invention, a level-converting method comprises the steps of outputting a level converting signal having a different level from that of an input signal in response to an input signal, delaying the level converting signal by a predetermined delay time, and generating a reset signal in response to the delayed level converting signal and controlling the level converting signal by the reset signal so that a pulse width of the level converting signal as output is set as much as the sum of the predetermined delay time and an internal operational delay time.
According to an aspect of the invention, a signal converting method that is appropriate for a semiconductor device, comprises the steps of receiving through each separate paths a first input signal and a second input signal that are input as differential input signals, separately generating pulse types of first and second converting signals in response to each shifts of the first and second input signals, and outputting a single ended signal as an output signal having a pulse width corresponding to pulse widths of the first and second input signals in response to the first and second converting signals.